In the past, a scan test including, for example, level-sensitive scan design (LSSD) has been conducted on a manufactured circuit including a large scale integrated circuit (LSI) or the like. Methods for conducting the scan test are briefly described.
When conducting the scan test, every flip-flop (hereinafter referred to as an “FF”) provided in a circuit targeted for verification is replaced by a scan FF including a scan latch and a scan interface, and the scan interfaces of the scan FFs are serially connected to one another via a path referred to as a “scan chain”. Then, data is transmitted from a scan input of the scan interface of a predetermined scan FF and a shift operation is performed so that data is set to each of the scan FFs. The above-described data set to each of the scan FFs becomes data of an expected value. Then, scan shifting is performed to compare data transmitted from a scan output of the scan interface of the scan FF to the expected value data so that the circuit is inspected.
The above-described method can be performed at low cost. However, when a fault occurs, it is difficult to determine the fault occurrence spot through the above-described method. Consequently, it is difficult to determine in which part of the manufacturing process a problem occurs. In recent years, therefore, methods for setting an expected value for the scan FF have been devised. The methods include, for example, the method of providing a pin used to set data “0” to the scan FF in each of scan FFs so that an expected value “0” is set to each of the scan FFs when the power is turned on. The above-described method allows for determining the fault occurrence spot based on a difference between data transmitted from the scan output and the expected value.
The above-described method of setting the data “0” to the scan FF allows for detecting the fault occurrence spot when a “stuck-at-1 fault” occurs so that the expected value “0” set to the scan FF is changed to a value “1”. However, the method does not allow for detecting the fault occurrence spot when a “stuck-at-0 fault” occurs so that the expected value “1” is changed into a value “0”. Therefore, the method of providing a pin used to set data “1” to the scan FF in addition to the pin used to set the data “0” to the scan FF so that the data “0” and/or the data “1” is set to each of the scan FFs when the power is turned on has been devised. The above-described method allows for determining the spots where the “stuck-at-1 fault” and the “stuck-at-0 fault” had occurred.
However, a problem of the above-described known technologies is that a circuit scale using the above-described method becomes larger. More specifically, when the above-described known technologies are used, the pin used to set the data “0” and that used to set the data “1” are provided for each of the scan FFs to determine the spots where the “stuck-at-1 fault” and the “stuck-at-0 fault” had occurred. Particularly, since the pin used to set the data “1” is not usually provided for existing scan FFs, the circuit scale is increased to detect the “stuck-at fault 0”.
Further, in addition to the above-described technologies, a method of analyzing the fault occurrence spot through software has been devised. When output data is degenerated due to a fault, the above-described method allows for propagating value data transmitted from the scan input onto the scan chain with no faults by applying the system clock pulse. Then, the result of measuring the propagated value data is compared to logic simulation data obtained by transmitting data of the degeneration fault onto the scan chain so that the spot where the degeneration fault had occurred is determined. However, depending on the fault occurrence spots, it has often been difficult to determine a scan FF where the fault had occurred.